1. Field of the Invention
The present invention relates to a high-precision analog switch that is used for a chopper-type comparator.
2. Description of the Related Art
FIG. 2 of the attached drawings illustrates a basic configuration of a chopper-type comparator. FIG. 3 of the attached drawings is a circuit diagram of a conventional analog switch that is used in this chopper-type comparator.
As shown in FIG. 2, the chopper-type comparator includes analog switches (SW) 1 and 2 for accepting an input signal VIN or a reference voltage VREF in accordance with a clock signal CLK. One of the switches 1 and 2 is selected by the clock signal CLK. The chopper-type comparator also includes a capacitor 3 and inverter 4 that are serially connected to each other. The capacitor 3 is connected to the outputs of the analog switches 1 and 2. The chopper-type comparator further includes an analog switch 5 for establishing a short circuit between the input and output of the inverter 4 in accordance with the clock signal CLK.
The analog switches 1, 2, and 5 all have the same circuit constitution, and are constituted by a P-channel MOS transistor (called ‘PMOS’ hereinbelow) 11 and an N-channel MOS transistor (called ‘NMOS’ hereinbelow) 12 connected between terminals A and B, as shown in FIG. 3. The bulk of the PMOS 11 is connected to a power supply VDD and the bulk of the NMOS 12 is connected to ground potential GND. The gates of the PMOS 11 and NMOS 12 are connected to terminals EB and E respectively so that complementary clock signals CLKB and CLK are supplied to the gates of the PMOS 11 and NMOS 12 respectively. The clock signals CLKB and CLK are supplied to the analog switches 1, 5 and the analog switch 2 so that when the analog switches 1, 5 are turned on, the analog switch 2 is turned off, and vice versa.
With this chopper-type comparator, when the clock signal CLK is at level “H” or high level, the analog switches 1 and 5 are turned on and the analog switch 2 is turned off. As a result, the node N1, which is the input of the capacitor 3, has the input voltage VIN, and the nodes N2 and N3, which are the input and output of the inverter 4 respectively, have the threshold voltage VTH of the inverter 4. Accordingly, charging takes place such that the voltage between the output and input of the capacitor 3 becomes VTH−VIN.
When the clock signal CLK is at the level “L” or low level, the analog switches 1 and 5 are turned OFF and the analog switch 2 is turned ON. As a result, the potential of the node N1 is the reference voltage VREF and hence the potential of the node N2 is VTH−VIN+VREF because the voltage charged to the capacitor 3 is added. The potential of the node N2 is supplied to the inverter 4, which constitutes a comparator circuit. Hence, if this potential is higher than the threshold voltage VTH, that is, if VIN<VREF, the output signal OUT from the inverter 4 is “L”. If VIN>VREF, the output signal OUT is “H”.
When the analog switch 5 of the chopper-type comparator is in the OFF state, a parasitic diode D1 is formed between an N+ region, which is the drain of the PMOS 11, and a Psub substrate constituting the ground potential GND, as indicated by the dotted line in FIG. 3. Likewise, a parasitic diode D2 is formed between a P+ region, which is the drain of the NMOS 12, and a bulk N well, which is the supply potential VDD.
As a result, when the clock signal CLK is “L”, the analog switch 5 is OFF, and the potential of the node N2 (=VTH−VIN+VREF) is higher than the supply potential VDD, then the parasitic diode D1 is in the forward-biased direction and the electric charge accumulated in the capacitor 3 is discharged, whereby the potential of the node N2 fluctuates. When the potential of the node N2 is lower than the ground potential GND, then the parasitic diode D2 is ON in the forward-biased direction and hence the electric charge accumulated in the capacitor 3 is discharged, whereby the potential of the node N2 fluctuates. Therefore, in the chopper-type comparator that uses conventional analog switches, the input voltage VIN must satisfy the following condition so that the parasitic diodes D1 and D2 of the analog switches are not turned ON:VREF−VTH<VIN<VREF+VTH